A data communication system that employs Frequency Division Multiplexed (FDM) sub carriers for transmission of data across a communication channel is termed a multi-carrier communication system. A data communication system generally has a remote transceiver, such as a central office (CO) side modem and a local transceiver, such as a customer premise (CP) side modem. A transceiver generally has both the transmitter and the receiver.
In a data communication system, the remote and local transceivers have independent sampling clocks running their digital-to-analog converter (DAC) and analog-to-digital converter (ADC) clocks. The remote transceiver, in addition to having a DAC, also has an ADC to receive analog waveforms transmitted by the local transceiver. Similarly, the local transceiver, in addition to having an ADC, also has a DAC to transmit analog waveforms to the remote transceiver. The same clock signal drives both the DAC and ADC clocks of a given transceiver, and thus the DAC and ADC clocks of any given transceiver have a fixed phase relationship with each other. Changing the ADC clock phase by a certain amount on the local transceiver side also changes the clock phase by the same amount on the corresponding DAC on the local transceiver side. The same is true for the DAC and ADC clocks in the remote transceiver side.
The problem with such a data communication system is that it is generally difficult to provide synchronization between the ADC and DAC clocks running on the local transceiver side and the ADC and DAC clocks running on the remote transceiver side. As mentioned above, correcting the clock on only one side, for example, on the local transceiver side, automatically provides synchronism between the clock on the remote transceiver side and the clock on the local transceiver side. Therefore, clock correction can be applied to either the remote transceiver or the local transceiver alone. Such a system of clock correction is generally referred to as “loop timing”. The problem of loop timing, i.e. synchronization, is complicated by the presence of noise in the channel of a data communication system. Additional impairments like drift in the clock frequencies at either transceiver side or clock jitter, can further compound the clock synchronization problem.
The problem of clock synchronization in data communication systems generally stems from a mismatch between remote transceiver and local transceiver clock frequencies. Loss of clock synchronization typically leads to a loss of frame boundary synchronization, sample slippage, and a higher noise around received signals. These can in turn lead to higher rates of bit errors and a decreased data throughput.
Current solutions to the problem of clock synchronization are based on estimating relevant clock parameters of the system, such as clock drift rate and jitter statistics, and correcting for the same. Corrections for clock mismatch are typically through the manipulation of the clock frequency of the local clock. Many of the current solutions for clock synchronization effect through the use of Phase Lock Loop (PLL) hardware. One such method is disclosed in the U.S. Pat. No. 6,577,690, entitled “Clock recovery in multi-carrier transmission systems”. The scheme uses a frequency offset estimator. (Frequency offset here is referred to a “rate of drift of phase”. The estimator used to estimate the frequency offset is herewith also referred to by one or more of the following terms “frequency drift estimator” or “frequency estimator”. These terms should be taken to mean the one and same thing that is the “frequency offset estimator”. The terms “phase drift estimator” and “phase estimator” are used interchangeably and both refer to the same thing), whose output is used to correct the frequency of the local sampling clock. The scheme accounts for only frequency differences between the remote and local transceiver clocks, whereas in practice it is observed that frequency drift also results in a phase drift with respect to the remote transceiver clock. This phase drift is of a magnitude and rate that, if uncorrected, could lead to sample slippage and thus loss of synchronism and consequently sub-optimal performance of the modem. For example, U.S. Pat. No. 5,228,062 to John A. C. Bingham discloses a method and apparatus for correcting for clock and carrier frequency offset and phase jitter in multi-carrier modems which involves directly estimating various clock parameters, such as frequency offset, phase jitter and jitter frequency, and so on. The approach disclosed in this patent serves to correct for the effects of phase jitter, jitter frequency, and other clock parameters by fitting a model to these impairments.
Current solutions to the synchronization problem for data communication systems are generally based on correcting frequency differences between the remote and local transceiver clocks. However, in practice it is observed that due to a drift in frequency in the remote and local transceivers, there is also a drift in phase between the remote and local transceiver clocks. This phase drift is of such a magnitude and rate that if left uncorrected, could lead to sample slippage and thus lead to a loss of synchronization between the remote and local transceiver clocks, and consequently result in sub-optimal performance of the modems.
Therefore, there is a need to synchronize the remote and local transceiver clocks by correcting for both the frequency and phase drifts between the remote and local transceiver clocks, to improve performance of the modems in a data communication system.